1. Field of the Invention
This invention relates to a data processor having a branch instructions processing mechanism capable of suppressing disturbances in the pipeline processing, thereby providing high processing capability by means of effective operation of a multistage pipeline processing mechanism.
2. Description of the Prior Art
FIG. 1 is an example of schematic diagram of a pipeline processing mechanism used for a conventional data processor.
Reference numerals in the figure designate the following elements: 11, instruction fetch stage (IF stage); 12, instruction decoding stage (D stage); 13, operand address calculation stage (A stage); 14, operand fetch stage (F stage); and 15, instruction execution stage (E stage).
The IF stage 11 fetches instruction code from a memory and outputs it to the D stage 12. The D stage 12 decodes the instruction code received from the IF stage 11 and outputs a decoding result to the A stage 13.
The A stage 13 calculates an effective address of operand designated in the instruction code, and then outputs the calculated operand address to the F stage 14. In accordance with the operand address delivered from the A stage 13, the F stage 14 fetches an operand from memory. The fetched operand is delivered to E stage 15. The E stage 15 executes arithmetical operation designated by instruction code for the operand delivered from the F stage 14. It also stores the result of arithmetical operation in memory as required.
The pipeline processing mechanism mentioned above divides the processings designated by each instruction into five stages. By sequentially executing five-step processings, all the designated processing are completed. Each of five processings can be implemented in parallel with each other against different instructions. Ideally, compared to the case where no pipeline processing is executed, the five-stage pipeline processing mechanism mentioned above simultaneously processes five instructions so that an efficient data processor having a maximum of 5-times data processing capability can be provided.
As mentioned above, the pipeline processing mechanism has a possibility of greatly promoting data processing capability of data processors, and thus, is widely made available for achieving high-speed data processing operation.
Nevertheless, even the pipeline processing mechanism still has problems to solve. Actually, instructions are not always processed in ideal conditions. One of these critical problems is the method of executing branch instruction which easily disturbs the sequence of instructions.
The conventional data processor having the pipeline processing mechanism shown in FIG. 1 causes pipeline to be disturbed significantly when executing branch instructions by allowing the IF stage 11 to fetch the branch target instruction.
FIG. 2 shows the stage of instruction flows through pipeline when branch instructions are executed in the conventional data processor. In FIG. 2, instructions IN 3 and IN 12 are branch instructions. When instruction IN 3 is executed, whole instructions IN 4 through IN 7 under pipeline processing operation are canceled, and as a result, the IF stage 11 starts to process instruction IN 11. If this occurs, the time enough to process four instructions is wasted in the period from the execution of the instruction IN 3 via the E stage 15 to the execution of the instruction IN 11 by the E stage 15. Likewise, the time enough to process four instructions is wasted before executing the instruction IN 12. Only after completing all the pipeline processings for branch instruction, fetching of instruction to be processed after execution of branch instruction is executed by any conventional data processor, thus eventually resulting in the wasted time. The more the number of pipeline processing stages, the more the time being wasted.
It has been pointed out many times that the processing of branch instructions is a key point in improving the processing capacity of a data processor which performs pipeline processing, and various approaches have been attempted in this regard.
An example of branch instructions processing method is reported in J. K. F. Lee, A. J. Smith, "Branch Prediction Strategies and Branch Target Buffer Design", IEEE Computer, Vol. 17, No. 1, January, 1984. However, any of these proposed methods has drawbacks such as a requirement for a large hardware construction and validity restricted only to a part of the branch instructions.